As the demand grows in the industry for miniaturized high performance semiconductor packages, the need to manufacture a reliable high density interconnect structure for mounting semiconductors becomes increasingly important. Producing an interconnect structure having the largest number of chip connections over the smallest possible area is an important objective. It is also important to produce a structure capable of providing adequate wiring capabilities to take advantage of the high density connections.
FIG. 1 shows a much enlarged view, in elevation, of a prior art semiconductor chip carrier 10. The chip carrier 10 includes a substrate 12, a plurality of plated through holes 14, and a layer of conductive material 16 positioned on the side wall of each of the plated through holes and on portions of the surface of substrate 12. The conductive material 16 on portions of the surface of substrate 12 form connection pads 18. A first dielectric layer 20 is positioned on the exposed surface of substrate 12 and on portions of the layer of conductive material 16. The first dielectric layer 20 includes interconnection contact areas 22, which facilitate electrical connection of semiconductor chips (not shown), through interconnections (also not shown), to connection pads 18 of the plurality of plated through holes 14.
FIG. 2 shows a top view of a portion of semiconductor chip carrier 10. The connection pads 18 are dogbone shaped and consume a large portion of the surface area on the carrier 10. This is because each interconnection contact area 22, the area upon which the semiconductor chip interconnection is mounted, is offset from its corresponding plated through hole 14. As a result, the density of plated through holes 14 and interconnections between the semiconductor chip and interconnect contact areas 22 for each carrier 10 is limited.
Additionally, due to differences in the coefficient of thermal expansion between the semiconductor chip carrier, the chips and the interconnections therebetween, internal stresses develop within the semiconductor package during thermal cycling, which may eventually lead to interconnection or device failure.
As a result, there exists a need in the industry for a more reliable, compact interconnect structure which overcomes the disadvantages of known structures.